The trend in integrated circuit (IC) fabrication is to incorporate more and more circuitry on a single IC chip and to simultaneously improve the performance of the circuit. Scaling of device dimensions is the key for the success and enormous momentum of this semiconductor industry trend. Simple scaling of all device dimensions, reducing feature size and spacing, however, is increasingly difficult to achieve because physical limitations hinder further reduction.
One important dimension that must be considered in the scaling process is the depth and lateral extent of doped regions. Ion implantation is the process of choice for forming doped regions because of its high accuracy, reproducibility, and ability to provide very high concentrations of dopants in shallow layers. The ideal is a “diffusionless” transistor that allows a reduction of lateral device dimensions for high packing density circuits. The diffusionless transistor is difficult to realize, even with ion implantation, however, because the implanted dopant ions must be annealed. Annealing is required both to activate the implanted ions and to heal defects caused by the implantation process. Techniques have been developed to activate the implanted ions with minimal diffusion of the implant profile, for example by millisecond annealing, but such techniques are difficult to employ, require additional processing steps, and are not effective for healing defects. Additionally, such techniques are not compatible with the usual stress application techniques used to enhance device performance.
Accordingly, it is desirable to provide methods for integrated circuit fabrication that are compatible with device scaling. In addition, it is desirable to provide methods for fabricating ICs that have controlled dopant profiles and that are compatible with stress elements for performance enhancement. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.